Commits
Patrick Delaunay committed 0cb1aa94093
stm32mp1: ram: increase the delay after reset to 128 cycles Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>