uboot-phytec

MLK-14878 qspi: Fix issue when enabling DDR mode

There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
   won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
   cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
   like DDR_EN are cleared during these operations.  When we using DDR mode QSPI boot, the TDH bit
   is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
   So these operations will fail.
   The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
   after using DDR mode QSPI boot on 6UL/ULL EVK boards.

Signed-off-by: Ye Li <ye.li@nxp.com>