uboot-phytec

armv8: ls1046aqds: Adjust IFC timing for NOR flash

Increase setup, assertion and hold time related to chip-select signal.
Additional delay is needed for the signal to propogate through FPGA.
This adjustment slightly increase the read and write cycle but has no
impact on burst read or write.

Signed-off-by: York Sun <york.sun@nxp.com>