Commits
Siva Durga Prasad Paladugu committed 71723aaec5e
fpga: zynq: Add delay after PCFG_PROG_B change There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>