uboot-phytec

AM65SW-222 drivers: usb: dwc3: dwc3-generic: add support for SERDES PHY configuration

The default setting of the TI AM65x register CTRLMMR_SERDES0_CTRL
LANE_FUNC_SEL field selects USB3 as the SERDES0 lane function.
This setting breaks USB 2.0 High Speed support on USB0 and, since
USB 3.x support is broken on AM65x silicon revision 1.0
(see TI AM65x/DRA80xM errata advisory i2028), we need a way to
configure this register field if SERDES0 is not being utilized
for PCIe0 or SGMII.

Added support for utilizing the U-Boot PHY framework to set this field.
This requires a 'phys' entry in the 'dwc3_0' node that points to a
phandle with two arguments as well as a 'phy-names' entry that
points to a "serdes-phy" string.

Example:
  phys = <&serdes0 PHY_TYPE_PCIE 1>;
  phy-names = "serdes-phy";

The first argument to the 'phys' phandle must be PHY_TYPE_PCIE or
U-Boot's SERDES driver will not allow the use of the PHY. The second
argument to the 'phys' phandle must be 1 or 2 for USB0 to function.

Signed-off-by: Matt McKee <mmckee@phytec.com>