Commits
Sagar Shrikant Kadam committed 8836384c754
riscv : serial: use rx watermark to indicate rx data is present In y-modem transfer mode, tstc/getc fail to check if there is any data available / received in RX FIFO, and so y-modem transfer never succeeds. Using receive watermark bit within ip register fixes the issue. This patch is based on commit c7392b7bc4e1 ("Use the RX watermark interrupt pending bit for TSTC") available at[1] [1] https://github.com/sifive/HiFive_U-Boot/tree/regression Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>