Commits
Rick Chen committed 8ba595b6bda
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>