Commits
Matt McKee committed 9f60ca69f7d
AM65SW-222 arm: dts: k3-am65xx-pcm-941: set USB0 PHY to serdes0 Set USB0 PHY to serdes0 to configure the CTRLMMR_SERDES0_CTRL register LANE_FUNC_SEL field to PCIe0 Lane0. If this field is left at its default USB 3.0 setting, USB 2.0 High Speed mode will not work on USB0. This workaround is necessary because USB 3.x support is broken on the AM65x v1.0 silicon revision. USB0 is configured for USB 2.0 mode, but since the PHYTEC phyCORE-AM65x Kit does not utilize SERDES0 for PCIe0 or SGMII, the LANE_FUNC_SEL is never changed from default and breaks USB0. Signed-off-by: Matt McKee <mmckee@phytec.com>