uboot-phytec

MLK-17239 mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the actual clock rate is just half of the expected clock.

This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 2a8a0cf0f5d2fcb06d217e3d026219532fed5eb7)
(cherry picked from commit c340cddc28f7a314ae52add5d934c7194a83404c)