Commits
Thierry Reding committed bca7910b7da
ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210 On Tegra210 the parents for the disp1 and disp2 clocks are slightly different from earlier chips. Only pll_p, pll_d_out0, pll_d2_out0 and clk_m are valid parents (technically pll_d_out is as well, but U-Boot doesn't know anything about it). Fix up the type name and the mux definition. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>