uboot-phytec

mtd: spi: spi-nor-core: Introduce support for calibrating controller

Certain SPI controllers have PHY which needs to be calibrated to work in
high frequency Octal DDR mode. Calibration generally involves tuning PHY
parameters until controller is able to read correct data from flash.
This would require to read pre defined data so as to compare during
calibration sequence. SFDP tables provide such predefined data.
Read SFDP at lower speed and in 1 bit mode and then pass this data to
driver to use during calibration sequence. Also, switch highest possible
8 bit DDR mode and tweak opcodes before calling calibration callback.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>