Commits
Vignesh Raghavendra committed c14f3c31112
board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build AM654 SoC is IO coherent wrt A53 cores, therefore enable SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>