uboot-phytec

MLK-12436-2: mx6qarm2: update ddr scripts

ALign with imx_v2015.04.
Also to lpddr2 support:
From commit: "620cf5f3d4cf37b065b5857a8ea91d61bf6c471d"
"
Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board,
but there is a problem in switching pre_periph_clk_sel to pll2_pfd2.
We cannot directly change the parent of pre_periph_clk_sel as this mux
is not a glitchless mux. We need to follow the correct procedure and wait
for the busy bits to clear before switching.
Change to follow the procedure:
1. Set periph_clk2 to OSC.
2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for
periph_clk , ahb_podf and axi_podf busy bits.
3. Setting the pre_periph_clk to PLL2 PFD 396M.
4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR
busy bits.
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
(cherry picked from commit febf98c68853030ce5c1f9124e77d75456e71314)