uboot-phytec

MLK-13450-15 ehci-mx6: Add powerup_fixup implementation

When doing port reset, the PR bit of PORTSC1 will be automatically
cleared by our IP, but standard EHCI needs explicit clear by software. The
EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it
clear the PR bit by writting to the PORTSC1 register with value loaded before
setting PR.

This sequence is ok for our IP when the delay time is exact. But when the timer
is slower, some bits like PE, PSPD have been set by controller automatically
after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite
these bits set by controller. And eventually the driver gets wrong status.

We implement the powerup_fixup operation which delays 50ms and will check
the PR until it is cleared by controller. And will update the reg value which is written
to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay
time to be accurate and aligining with controller's behaiver.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8dfdf83abaff44efb487f801cd1757a729d427c5)