disk: part: don't check ubifs mount in SPLWithout this change, enabling environment support in SPL
at the same time CMD_UBIFS is enabled breaks compilation.
Signed-off-by: Matt McKee <mmckee@phytec.com>
arm: mach-k3: am6_init: expose spl_boot_device() to non-SPLThis change needed to use spl_boot_device() in
env_get_location() which enables dynamic environment
saving and loading.
Signed-off-by: Matt McKee <mmckee@phytec.com>
SUBOOT-50 power: regulator: tps62360_regulator: add VDD pin regulator support for phyCORE-AM65xThis regulator is required for Adaptive Voltage Scaling
support on the phyCORE-AM65x.
Signed-off-by: Matt McKee <mmckee@phytec.com>
AM65SW-219 arm: dts: k3-am65xx-pcm-941: enable USB1 supportUSB1 is enabled in peripheral mode to allow Android fastboot.
Signed-off-by: Matt McKee <mmckee@phytec.com>
AM65SW-222 arm: dts: k3-am65xx-pcm-941: set USB0 PHY to serdes0Set USB0 PHY to serdes0 to configure the CTRLMMR_SERDES0_CTRL register
LANE_FUNC_SEL field to PCIe0 Lane0. If this field is left at its
default USB 3.0 setting, USB 2.0 High Speed mode will not work on USB0.
This workaround is necessary because USB 3.x support is broken on the
AM65x v1.0 silicon revision. USB0 is configured for USB 2.0 mode, but
since the PHYTEC phyCORE-AM65x Kit does not util...
AM65SW-222 drivers: usb: dwc3: dwc3-generic: add support for SERDES PHY configurationThe default setting of the TI AM65x register CTRLMMR_SERDES0_CTRL
LANE_FUNC_SEL field selects USB3 as the SERDES0 lane function.
This setting breaks USB 2.0 High Speed support on USB0 and, since
USB 3.x support is broken on AM65x silicon revision 1.0
(see TI AM65x/DRA80xM errata advisory i2028), we need a way to
configure this register field if SERDES0 is not being utilized
for PCIe0 or SGMII.
...
AM65SW-241 drivers: net: phy: ti: add additional LED config optionsNew device tree properties added to support further LED
configuration. The following properties have been added:
ti,led-0-active-low: invert the polarity of LED_0
ti,led-2-active-low: invert the polarity of LED_2
If the one or both of the above properties are not present in the PHY
node, the default of active high will be used for the respective LEDs.
These changes were tested on the PHY...
AM65SW-41 drivers: ram: k3-am654-ddrss: add support for S3 and S5 supply regulatorsNew device tree properties added to support multiple DDR4 termination
supply regulators. The following entries must point to a valid
regulator node for the PHYTEC phyCORE-AM65x SOM:
ddr-s3-supply: supply regulator that drives the S3 control signal
ddr-s5-supply: supply regulator that drives the S5 control signal
Signed-off-by: Matt McKee <mmckee@phytec.com>
Revert "ram: k3-am654: add support for LPDDR4 and DDR3L DDRs"This reverts commit c78ac7a0c911da33683b8d88965a910b2dcbd144.
Revert is needed to use known-working DDR configuration while
problems with driver updates and new configuration are debugged.
Revert "ram: k3-am654: Do not rely on default values for certain DDR register"This reverts commit 34f27b2e86b996483be30d05e3c753a4fc055adf.
Revert is needed to use known-working DDR configuration while
problems with driver updates and new configuration are debugged.
AM65SW-149 arm: mach-k3: arm64-mmu: increase NR_MMU_REGIONSWhen configuring the MMU, the am654_mem_map array is traversed until
size and attrs fields are both zero. This leads to an out-of-bounds
memory access and potential MMU misconfiguration when am654_mem_map is
not large enough to contain the list terminator. To fix this, we
guarantee am654_mem_map is large enough by increasing NR_MMU_REGIONS
to account for cases where CONFIG_NR_DRAM_BANKS is less...
AM65SW-21 am65xx-phycore-kit: add files from TI as development base* board/phytec/am65xx_phycore_kit/ sourced from board/ti/am65x/
* include/configs/am65xx_phycore_kit.h sourced from
include/configs/am65x_evm.h
* configs/am65xx_phycore_kit_a53_defconfig and
am65xx_phycore_kit_r5_defconfig sourced from
configs/am65x_evm_a53_defconfig and am65x_evm_r5_defconfig
Signed-off-by: Matt McKee <mmckee@phytec.com>
tools: k3_fit_atf: fix FIT image ordering for UART bootYmodem is pretty picky about the ordering of the images, causing a boot
failure if images are in wrong order. SPL must be the last image loaded
in the loadables list, as any images post it are effectively ignored.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: sysfw-loader: Correct value used in type fieldThe INDEX value was mistakenly used in the type field instead of the
value corresponding to the TISCI MSG for the type of boardcfg being
shared, so correct this.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
firmware: ti_sci: Update ti_sci_msg_req_reboot to include domainThe ti_sci_msg_req_reboot message payload has been extended to include a
domain field, but for the purposes of u-boot this should be zero to
reset the entire SoC as it did before. Include domain for completeness
and set to zero to ensure proper operation.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
arm: mach-k3: security: do not check images with zero sizeIf DM image is not built-in to the fit, its size is going to be zero.
In this case, do not attempt to authenticate it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: common: fix build failure for HS devicesHSM rearch support series inadvertently broke HS build. Fix by removing
the offending piece of code conditionally via config flags.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: sysfw-loader: pass boardcfg to sciserverCopy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
configs: j7200_evm_r5: Enable raw access power management featuresSysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[praneeth@ti.com: rebased patch to current ti-u-boot-2020.01]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
configs: j721e_evm_r5: enable FIT image post processingThis is used to parse the images from FIT, and to determine image types.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
configs: j721e_evm_a72: disable watchdogDisable early boot watchdog as it is not really needed for anything
right now.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[praneeth@ti.com: rebase the patch to current ti-u-boot-2020.01]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
configs: j721e_evm_r5: disable SCI PM driversWith the sysfw rearch, PM services are no longer available for R5 SPL to
use. Instead, we will be using the raw PM register level access drivers
for any PM. Thus, disable the SCI PM drivers to reflect this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
configs: j721e_evm_r5: Enable raw access power management featuresSysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: do board config for PM and RM only if supportedIf the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: j721e: force enable A72 core 0 during spl shutdownWith the new raw register mode access PM drivers, A72 core is not
enabled via ti-sci services, leading into bad usecounts for the core.
This effectively shuts down the A72 core when SPL goes down. Prevent the
problem by force enabling the A72 core once, which increases the use
count.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: add support for detecting firmware images from FITAdd callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Matt McKee
Tero Kristo
Dave Gerlach