TI Processor SDK RTOS
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csl-phytec

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AuthorCommitMessageCommit dateIssues
Matt McKeeMatt McKee
63aaa827571example: dcan: dcanLoopback: add support for PHYTEC phyCORE-AM572x RDKThis patch facilitates support for the CAN1 and CAN2 interfaces on the PHYTEC phyCORE-AM572x RDK by allowing pinmuxing at the board support level to take precedence over a hardcoded configuration. Internal reference: AM57TRTOS-21 AM57TRTOS-1 Signed-off-by: Matt McKee <mmckee@phytec.com>2 Jira Issues
Aravind BatniAravind Batni
852cfe681c7Address PRSDK-4790Signed-off-by: Aravind Batni <aravindbr@ti.com>PRSDK-4790
DhandeDhande
0c3b2c8a054[MCAN App]Added support for Maxwell EVM- Application now runs on Maxwell EVM - Added PAD configurations - Minor changes in App to add support for Maxwell - changed earlier UART print functions, added extra layer to have this abstraction Signed-off-by: Dhande <v-dhande@ti.com>
Sivaraj RSivaraj R
8acccc27b09Migrated MCAN UT to use SCICLIENT- The ring size is in reg value and not in bytes - Leave as is to default value of init instead of overriding Signed-off-by: Sivaraj R <sivaraj@ti.com>
SunilSunil
6322c20b369Added MCAN IP specific macro Max Baud rate prescaler value in hw_mcanss.hSigned-off-by: Sunil <x0190988@ti.com>
Rishabh GargRishabh Garg
358f2fd42d4Bug fix: PDK-3230- Added typecast to uintptr_t Signed-off-by: Rishabh Garg <rishabh@ti.com>PDK-3230
Rishabh GargRishabh Garg
67821fb4292Fixed doxygen issuesSigned-off-by: Rishabh Garg <rishabh@ti.com>
Sinthu Raja MSinthu Raja M
e0d8a524fcdDoc/version update to 3.3.0.12
Sinthu Raja MSinthu Raja M
4b1ec9b6099PRSDK-729 Removed redundant K2G macroPRSDK-729
John DowdalJohn Dowdal
85712a42cdfPRSDK-3849: CSL modification to make arrays out of symbols thatare numbered in their name.PRSDK-3849
SunilSunil
47d4c798b1d[Added MCAN register SET/CLEAR macros]These macros are needed by MCAL CAN driver. Signed-off-by: Sunil <x0190988@ti.com>
DhandeDhande
105e43d25dc[PDK-2941]Exception Handler Register API_ Added 2 APIs for exception hanlders initializaion and configurationPDK-2941
DhandeDhande
8da4cab19bc[PDK-2963]R5 CSL: It shall support configuration of MAIN and MCU domian R5 VIM- VIM base address changes from MCU domain R5 to MAIN domain R5. This address is internal to R5 core hence R5 CSL FL shall take care populating this address internally. - Added API for the samePDK-2963
Sivaraj RSivaraj R
c6f37128b82[PDK-2977]: Added resume API for DRUSigned-off-by: Sivaraj R <sivaraj@ti.com>PDK-2977
Sinthu Raja MSinthu Raja M
86275a52016PRSDK-3310 Add OCMC ECC support for AM571x/2x Add OCMC ECC support for AM571x/2x with ECC example test enabled for validation. PRSDK-3310 Update Copyright banner Update copyright banner for CSL example PRSDK-3310 Add flags to track CSLR modification Add CSL_MODIFICATION flag to track manual update for CSLR files PRSDK-729 Add L1P/L2 EDC example for K1 and K2 devices Add EDC example support for K1 and K2 devices Add UART conso...3 Jira Issues
Rishabh GargRishabh Garg
3c7f8d7bab3Minor CSL updateSigned-off-by: Rishabh Garg <rishabh@ti.com>
William S EgrWilliam S Egr
43386b90d4bAdd J7 support to top-level csl_ospi.h file
Madan SrinivasMadan Srinivas
0662c2b2976PRSDK-4594: Removes superfluous API CSL_a53v8CleanInvalidateDcacheLineMvaPoC from header fileThe CSL_a53v8CleanInvalidateDcacheLineMvaPoC is unimplemented, but the header file lists it and can cause confusion. The same functionality is implemented by CSL_a53v8CleanInvalidateDcacheMvaPoC. This patch removes the superfluous definition from the header file. Signed-off-by: Madan Srinivas madans@ti.comPRSDK-4594
Gulur DwarakanathGulur Dwarakanath
6b94b55f2caFixed BTCM base address
Gulur DwarakanathGulur Dwarakanath
cc09b21af67Fixed IIRAM_SLV end address
Rishabh GargRishabh Garg
4556f4484caFixed doxygen warningsSigned-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
4713f49aabaDefined display buffers as const dataSigned-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
7d7da35c991PDK-2945 Used pixel inc while doing horizontal scalingSigned-off-by: Rishabh Garg <rishabh@ti.com>PDK-2945
Vibha PantVibha Pant
324f6c1e6e8PDK-2891: CSLR: GPIO Register Macros DefinitionCorrected the register macro definition for GPIO Using hexadecimal for conversion Signed-off-by: Vibha Pant <v-pant@ti.com>PDK-2891
Rishabh GargRishabh Garg
69edcb02716Fixed more MISRA for DSSSigned-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
37246929eaeChanged overlay get enabled layer API nameSigned-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
ae4d9dcb2fcMinor updatesSigned-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
6437bdae541CSL FVID2 datatypes update- Added macros instead of enums -Made corresponding changes to DSS CSL FL Signed-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
3b4d7b24983Added Video Mux API to J7 CSLSigned-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
5dd654daa46Added YUV422 SP for J7Signed-off-by: Rishabh Garg <rishabh@ti.com>
Rishabh GargRishabh Garg
5477347cf7aMISRA C fixes for DSS CSL FLSigned-off-by: Rishabh Garg <rishabh@ti.com>
Santosh JhaSantosh Jha
1368c1fcc81Modified hw_mailbox.h for mailbox register offset.- Validated on J7ES VLAB
Dasnavis SabiyaDasnavis Sabiya
3143639ae7fPRSDK-3403: Case correction in cslr_pmmc.h filePRSDK-3403
Dasnavis SabiyaDasnavis Sabiya
58d477396e7PRSDK-3403: Fixed CPP build errors- Updated function declarations to be CPP compatible - Removed additional CPP compatible macroPRSDK-3403
Dasnavis SabiyaDasnavis Sabiya
161ce78ebadPRSDK-3403: Fixed CPP build error on A15 corePRSDK-3403
Dasnavis SabiyaDasnavis Sabiya
845d49a82fePRSDK-3403: Updated CSL_IvaHdRegs structure to use C99 data typesPRSDK-3403
Dasnavis SabiyaDasnavis Sabiya
a8969ce31daPRSDK-3403: Fixed compilation issue while including header filesPRSDK-3403
Sivaraj RSivaraj R
37a81b9d680PDK-2927: RA API to just init structure- This is needed to integrate UDMA LLD with DMSC firmware as non-RT configuration is done via DMSC - Need to maintain state to use RT API like ring push and pop Signed-off-by: Sivaraj R <sivaraj@ti.com>PDK-2927
Misael Lopez CruzMisael Lopez Cruz
8db3d673101PDK-2909: Fix argument passed to CSL_vimAckIntrThe Intc_IntClrPend() function called CSL_vimAckIntr() to acknowledge that the interrupt has been serviced with the wrong argument. CSL_vimAckIntr() expects an interrupt map of type CSL_VimIntrMap, but the interrupt number but instead the interrupt was being passed. Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>PDK-2909
Dasnavis SabiyaDasnavis Sabiya
12db71f84ecuart: PRSDK-4197: UARTDivisorValCompute does not round up to nearest integerChange the way to compute the UART divisor value to round to the nearest integer to avoid large baud rate errors.PRSDK-4197
William S EgrWilliam S Egr
038ae51b295Add SOC_J7 and SOC_AM77X support to spinlock top-level CSL files
Sivaraj RSivaraj R
75af5b85411Fixed MISRAC violations- MISRA.CAST.CONST - MISRA.CAST.OBJ_PTR_TO_INT.2012 - MISRA.CAST.VOID_PTR_TO_INT.2012 Signed-off-by: Sivaraj R <sivaraj@ti.com>
Aravind BatniAravind Batni
09460bcf7d3PRSDK-4377: correct OCMC RAM size values for AM57x platformsSigned-off-by: Aravind Batni <aravindbr@ti.com>PRSDK-4377
Rishabh GargRishabh Garg
73cb1c0f7e0Fixed build issueSigned-off-by: Rishabh Garg <rishabh@ti.com>
Sivaraj RSivaraj R
a23a1312b26J7 build fix for SOC name change- DRU base addresses are missing - DSS base address name changed. So changed dss app to match the new name Signed-off-by: Sivaraj R <sivaraj@ti.com>
Rishabh GargRishabh Garg
917c836adf9Updated CSC coefficients and Minor comment update in DSS exampleSigned-off-by: Rishabh Garg <rishabh@ti.com>
Sivaraj RSivaraj R
78a5dccd9adAdded J7 mailbox buildSigned-off-by: Sivaraj R <sivaraj@ti.com>
William S EgrWilliam S Egr
5b67316065cFix maxwell ring monitor counts in navss defines header file
Rishabh GargRishabh Garg
bb9483ce002Change CSC range to fullSigned-off-by: Rishabh Garg <rishabh@ti.com>
William S EgrWilliam S Egr
8a199601986[cpts] Remove replicated information