usb-phytec

PRSDK-3040 Added memory alignment for OMAPL138 DSP

 - For loading DSP code through SBL, HOST1CFG register needs to be configured
   with DSP program entry point address after loading the program to DSP memory.
   Least significant 10 bits of this register are fixed at 0 by default and cannot
   be changed by software. So the DSP program entry point should be 1KByte aligned
   to initiate DSP code execution from ARM core