Commits
Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next * clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs
Showing diff tofc206543893
- Stephen Boyd committed b183c6887afMMerge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-renesas', 'cl...
- Paul Cercueil committed 2b555a4b9caclk: ingenic: Add missing flag for UDC clock The UDC clock of the JZ4740 SoC can be ga...
- Daniel Mack committed 33f5104624bclk: Add driver for MAX9485 This patch adds a driver for MAX9485, a programmable audio...
- Robert Jarzmik committed fc206543893clk: pxa: export 32kHz PLL This clock is especially used by the RTC driver, so export ...
- Lei YU committed cd88259a721clk: aspeed: Fix SDCLK name The SDCLK was named SDCLKCLK, and no one has used this yet...
- Anson Huang committed 9d8108f9f3cclk: imx6sll: add GPIO LPCGs According to Reference Manual Rev.0, 06/2017, there are G...