uboot-imx

MLK-14533 mx7ulp_evk: Change APLL and its PFD0 frequencies

To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since
the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is
201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources
from APLL PFDs are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must
change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12),
with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 91be2789a93288cc087cd9e8db522c8308ef007c)
(cherry picked from commit dba948539edd4611610d9f1fc3711d1d922262ae)
(cherry picked from commit b2842f99262f10ac6595d1350e2a97c2e92118c9)