configs: add support for PHYTEC phyCORE-AM57x SOMs with AM5729, 46, and 48 SOCsSupport added for the following phyCORE-AM57x SOM configurations:
PCM-057-10306111I
PCM-057-11304111I
PCM-057-11305111I
Internal references: SUBOOT-99 SUBOOT-100 SUBOOT-101
Signed-off-by: Matt McKee <mmckee@phytec.com>
board: phytec: am57xx_phycore_kit: add support for SOMs with AM5729, 46, and 48 SOCsSupport added for the following phyCORE-AM57x SOM configurations:
PCM-057-10306111I
PCM-057-11304111I
PCM-057-11305111I
Internal references: SUBOOT-99 SUBOOT-100 SUBOOT-101
Signed-off-by: Matt McKee <mmckee@phytec.com>
arm: dts: am57xx-phycore: add support for SOMs with AM5729, 46, and 48 SOCsSupport added for the following phyCORE-AM57x SOM configurations:
PCM-057-10306111I
PCM-057-11304111I
PCM-057-11305111I
Internal references: SUBOOT-99 SUBOOT-100 SUBOOT-101
Signed-off-by: Matt McKee <mmckee@phytec.com>
board: ti: beagleboneai: enable in am57xx_evm_defconfigAdding the configurations to the evm_defconfig file
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
board: ti: beagleboneai: add dts fileBeagleBoard.org BeagleBone AI is an open source hardware single
board computer based on the Texas Instruments AM5729 SoC featuring
dual-core 1.5GHz Arm Cortex-A15 processor, dual-core C66 digital
signal processor (DSP), quad-core embedded vision engine (EVE),
Arm Cortex-M4 processors, dual programmable realtime unit
industrial control subsystems and more. The board features 1GB
DDR3L, USB3.0 Ty...
board: ti: beagleboneai: IODELAY and pinmux changesThis patch configures the pinmux settings for the BeagleBone AI after
the emmc read has completed.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
board: ti: beagleboneai: add initial supportThese are necessities for beaglebone ai boot. There is the addition of
CONFIG_SUPPORT_EMMC_CONFIG to the Kconfig file. This is present upstream
but not in 19.01 yet.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
board: ti: beagleboneai: emmc read changesBeagleBoard.org BeagleBone AI rev A1 does not include a board
identifier I2C EEPROM due to a design oversight. These boards have
been put into production and are generally available now.
The board identifier information, however, has been included in the
second eMMC linear boot partition (/dev/mmcblk1boot1).
This patch works by:
* First, looking for a board identifier I2C EEPROM and if not fo...
arm: mach-omap2: dra7: Enable Timer14 for IPU1 OpenCL firmwareThe OpenCL IPU1 firmware uses GPTimer14 with EVEs, so enable the GPTimer14
as well during the early-enabling of the clocks associated with/used by
the IPU1 firmware. This fixes a l3_noc error seen with early-boot of
IPU1 OpenCL firmware.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
ARM: DRA7: Add PRCM clkctrl registers for missing GPTimersThe DRA7xx/AM57xx SoCs has more GPTimers (16) than the previous
generation OMAP4/OMAP5 SoCs (12). Add the PRCM clkctrl register
definition for GPTimers 13, 14, 15 and 16 so that they can be
enabled if needed in SPL or U-Boot for IPU/DSP early-boot
scenarios.
While at this, also add the missing register definitions for
GPTimers 5 and 6. These were added reusing the previous cm_abe
definitions e...
Merge pull request #10 in PROCESSOR-SDK/processor-sdk-u-boot from PLSDK-3155 to processor-sdk-u-boot-2019.01* commit 'a9001bbf7d24eb260647e29e747446dee9cae0ed':
arm: dts: k3-am654: add mii-rt phandle in icssg prueth DT nodes
net: ti: icssg-prueth: Add support for 100M links
Revert "arm: dts: k3-am654-r5-base-board: enable wkup_vtm0 node and link in supplies"This reverts commit f75f3feca8da47f8b3d0627c4e6923b344ab00df.
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
arm: dts: k3-am654: add mii-rt phandle in icssg prueth DT nodesTo allow configure MII RT interface TX_IPG0/1 values differently
for 100M link vs 1G link, add phandle for mii_rt regmap node
in icssg prueth DT nodes.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
net: ti: icssg-prueth: Add support for 100M linksCurrently driver doesn't set the speed and full duplex parameters
in RGMII CFG based on PHY auto negotiated parameters. This patch
make updates so that both 100M/1G link speed and full duplex are
configured in RGMII CFG register based on PHY negotiated values.
Also Firmware requires that minimum inter packet gap (TX_IPG0/1 field of
ICSSG_TX_IPG0/1 register) is to be set to desired values based...
Merge pull request #9 in PROCESSOR-SDK/processor-sdk-u-boot from PLSDK-3150 to processor-sdk-u-boot-2019.01* commit '8e7ad5c94d872f6fc312b35036707133ccffa4ee':
Revert "arm: dts: k3-am654: add support for interposer card."
Revert "net: ti: icssg-prueth: update for interposer card"
Merge tag 'ti2019.05-rc4' of git://git.ti.com/ti-u-boot/ti-u-boot into processor-sdk-u-boot-2019.01TI-Feature: ti_uboot_base-2019.01
TI-Tree: git://git.ti.com/ti-u-boot/ti-u-boot.git
TI-Branch: ti-u-boot-2019.01
ti2019.05-rc4
* tag 'ti2019.05-rc4' of git://git.ti.com/ti-u-boot/ti-u-boot:
arm: dts: dra7-ipu-common-early-boot: Limit IPU early boot to IPU1 only
arm: mach-omap2: dra7: Undo changes related to booting IPU2
arm: dts: am57xx*: Limit IPU early boot to only TI platforms
net:...
arm: dts: dra7-ipu-common-early-boot: Limit IPU early boot to IPU1 onlyThe dra7-ipu-common-early-boot.dtsi file has the necessary changes to
configure both the IPU1 and IPU2 remote processors for 'early boot' from
SPL. Remove the changes for IPU2 for the moment to limit the 'early boot'
mode for IPU1 _only_. This is being done due to the limitations with some
of the current IPU2 firmware files.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm: mach-omap2: dra7: Undo changes related to booting IPU2The early-boot feature is being limited to IPU1 _only_ at the moment,
so undo the hard-wired code that enables the needed clocks and performs
the necessary steps to load and boot the IPU2 remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm: dts: am57xx*: Limit IPU early boot to only TI platformsThe commit e273b151d17f ("arm: dts: am57xx*: Add ipu early boot DT
changes") has refactored the IPU early boot changes into a separate
dtsi file. Limit this early boot feature to only TI platforms as this
feature requires the corresponding late-attach changes to be applied
to the respective kernel platform dtsi files. These changes were not
not added to the CompuLab CL-SOM-AM57x and SBC-AM57x b...
SUBOOT-50 power: regulator: tps62360_regulator: add VDD pin regulator support for phyCORE-AM65xThis regulator is required for Adaptive Voltage Scaling
support on the phyCORE-AM65x.
Signed-off-by: Matt McKee <mmckee@phytec.com>
AM65SW-219 arm: dts: k3-am65xx-pcm-941: enable USB1 supportUSB1 is enabled in peripheral mode to allow Android fastboot.
Signed-off-by: Matt McKee <mmckee@phytec.com>
AM65SW-222 arm: dts: k3-am65xx-pcm-941: set USB0 PHY to serdes0Set USB0 PHY to serdes0 to configure the CTRLMMR_SERDES0_CTRL register
LANE_FUNC_SEL field to PCIe0 Lane0. If this field is left at its
default USB 3.0 setting, USB 2.0 High Speed mode will not work on USB0.
This workaround is necessary because USB 3.x support is broken on the
AM65x v1.0 silicon revision. USB0 is configured for USB 2.0 mode, but
since the PHYTEC phyCORE-AM65x Kit does not util...
AM65SW-222 drivers: usb: dwc3: dwc3-generic: add support for SERDES PHY configurationThe default setting of the TI AM65x register CTRLMMR_SERDES0_CTRL
LANE_FUNC_SEL field selects USB3 as the SERDES0 lane function.
This setting breaks USB 2.0 High Speed support on USB0 and, since
USB 3.x support is broken on AM65x silicon revision 1.0
(see TI AM65x/DRA80xM errata advisory i2028), we need a way to
configure this register field if SERDES0 is not being utilized
for PCIe0 or SGMII.
...
AM65SW-241 drivers: net: phy: ti: add additional LED config optionsNew device tree properties added to support further LED
configuration. The following properties have been added:
ti,led-0-active-low: invert the polarity of LED_0
ti,led-2-active-low: invert the polarity of LED_2
If the one or both of the above properties are not present in the PHY
node, the default of active high will be used for the respective LEDs.
These changes were tested on the PHY...
Matt McKee
James Tsai
Jacob Stiffler
Caleb Robey
Jason Kridner
Suman Anna
Vivek Chengalvala
Jacob Stiffler
J, KEERTHY
Muralidharan Karicheri